The present invention relates to the field of integrated circuits and in particular, to architectures for memory within a programmable logic integrated circuit to improve performance.
Programmable logic integrated circuits such as PALs, PLDs, FPGAs, LCAs, and others are becoming more complex and continually evolving to provide more user-programmable features on a single integrated circuit. Modern programmable logic integrated circuits incorporate programmable logic including logic gates, products terms, or look-up tables. Programmable logic integrated circuits also included embedded user-programmable memory or RAM.
Despite the success of programmable logic, there is a continuing desire to provide greater functionality in a programmable logic integrated circuit, but at the same time, provide greater performance. There is a need to provide more higher performance user memories. Larger memory sizes or providing more memory blocks typically negatively impacts the performance of the integrated circuit because the integrated circuit is larger. There is programmable interconnect (e.g., GH and GV lines) will usually be longer and there will be greater capacitance. This reduces performance. It is desirable to have a high-speed interface and interconnections between the logic blocks and the memory blocks. Further, it is desirable to provide flexible stitching together or combining of the user memories in space-efficient and high performance manner.
Therefore, there is a need to provide high performance address decoding techniques and circuitry in order to improve the performance of the integrated circuit.
The present invention provides a high-performance programmable logic architecture with embedded memory. Memory blocks are arranged at the peripheries or edges of the integrated circuit so in order to shorten the lengths of the programmable interconnect. In a specific embodiment, the memory blocks are organized in memory block rows along the top and bottom edges of the integrated circuit. The memory blocks may also be organized in columns at the left and right edges for similar benefits. Each logic block is separated into a driver block and logic elements. Flip chip technology is used so IO bands for the integrated circuit are within the core of the integrated circuit; there are no IO bands between the memory blocks and the edges of the integrated circuit. The logic elements can be directly routed and connected to driver blocks and programmable routing resources of the logic block in adjacent rows and columns. This permits fast interconnection of signals without using the global programmable interconnect resources. Using similar direct programmable interconnections, the logic blocks can directly connect to the programmable routing resources of the memory blocks without using the global programmable interconnect resources. The present invention also provides technique of flexibly combining or stitching multiple memories together to form memories of a desired size.
In one embodiment, the invention is a programmable logic integrated circuit including a number of programmable interconnect lines arranged in rows and columns. There are a number of logic array blocks between rows and columns of the programmable interconnect lines, where the logic array blocks are arranged in rows and columns and programmably connected to the programmable interconnect lines, and the logic array blocks are programmably configurable to perform logical functions. A number of embedded array blocks are between rows and columns of the programmable interconnect lines, where the embedded array blocks are arranged in a row and each embedded array block includes a RAM block. The RAM block includes at least 2048 bits of memory. The logic array blocks include logic elements. Two embedded array blocks of a row can be programmably combined to provide a larger memory than available with a single embedded array block. A row of embedded array blocks comprises fifteen embedded array blocks. A row of embedded array blocks is programmably configurable to be one 30Kx1 memory, two 14Kx1 memories, three 10Kx1 memories, five 6Kx1 memories, or seven 4Kx1 memories.
The programmable logic integrated circuit may further include a decoder connected to receive a first address and generating a plurality of output control lines, each connected to an enable input one of the embedded array blocks. The output control lines are programmable interconnect lines. Some of the programmable interconnect lines are coupled to provide a second address-to-address inputs of the embedded array blocks. The first address comprises five bits. The second address comprises eleven bits.
In another embodiment, the invention is a programmable logic integrated circuit including a top row of memory blocks formed along a top edge of the integrated circuit and a bottom row of memory blocks formed along a bottom edge of the integrated circuit. A number of logic blocks are arranged in rows and columns and are programmably configurable to implement logic functions. The logic blocks are formed between the top and bottom rows of memory blocks. There are IO bands between the rows of memory blocks. In a specific flip chip implementation, there are no IO bands between the memory blocks and the edge of the integrated circuit. A number of horizontal programmable interconnect lines are programmably connected to the logic blocks. A number of vertical programmable interconnect lines are programmably connected to the logic array blocks. In a specific implementation, the vertical programmable interconnect lines do not extend an entire length from the top to bottom rows of the memory block. In particular, the vertical programmable interconnect lines extend from an inside edge of the top row of memory blocks to an inside edge of the bottom row of memory blocks.
The top row of memory blocks comprises six blocks or more of memory which can be programmably connected together to form larger memory blocks. The logic blocks are grouped into sections of logic blocks and between each section is an IO band. An IO band includes IO pads and input and output circuitry. Each section has three rows of logic blocks and at least forty columns of logic blocks. The programmable logic integrated circuit further includes a phase locked loop circuit formed along with the top row of memory blocks.
A logic block includes a number of logic elements and a driver block, where the number of logic elements is directly programmably connected to a driver block or programmable routing resources of an adjacent logic array block in the same row, without using the horizontal or vertical programmable interconnect. A logic block includes a number of logic elements and a driver block, where the number of logic elements is directly programmably connected to a driver block in an adjacent logic array block in an above row, without using the horizontal or vertical programmable interconnect. A logic block includes a number of logic elements and a driver block, where the number of logic elements is directly programmably connected to a memory block and in particular, the programmable routing resources, in the top row, without using the horizontal or vertical programmable interconnect.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.